In analog to digital signal converters employing sampling comparators, each input analog signal sample is simultaneously compared to a plurality of different reference signal levels to determine approximately what the sample amplitude is. One comparator of a type commonly used in the art is disclosed in U.S. Pat. No. 3,676,702 to E. P. McGrogan, Jr., the disclosure of which is hereby incorporated herein by reference. The determined amplitude value is then converted to a corresponding digitally represented, e.g., binary coded, value for such further utilization as may be appropriate.
It is well known that sampling comparators are subject to parasitic capacitance effects at their input connections. Those effects cause integral linearity error, sometimes called S-bow error, in the overall response characteristic of the digital to analog converter. That error is the cumulative effect of differential linearity error, resulting from the same parasitic capacitance effect, evident in each least significant bit (LSB) sized step of the characteristic. The problem of integral linearity error is described in greater detail, as "long term recovery error" and under the subheading "Accuracy'" in a paper by one of the inventors herein entitled "Monolithic Expandable 6 Bit 20 MHz CMOS/SOS A/D Converter" by A. G. F. Dingwall, IEEE Journal of Solid-State Circuits, Vol. SC-14, No. 6, Dec. 1979 pages 926-932. The problem will also be hereinafter further discussed to a limited extent in connection with disclosure of the present invention.
Some prior attempts to overcome the problems of integral linearity error have, as is pointed out in the aforementioned Dingwall paper, turned in the direction of providing a low-resistance reference supply voltage divider to supply the various levels of reference voltage required. Such a divider takes the form of a single, tapped, metal line; and divider current is so large that variations from ideal, caused by charging and discharging of the comparator parasitic capacitances, are essentially negligible. However, that large current involves correspondingly large power consumption. The latter factor is one to be avoided in present day systems design where one focus is on minimizing the cost and heat dissipation difficulties associated with large power consumption.